1. Field of the Invention
This invention relates to a video signal processing apparatus according to which input video signals are divided into plural channel signals for subsequent signal processing. More particularly, it relates to such apparatus according to which high-speed data signals obtained by sampling broad-band video signals such as high resolution video signals are converted into low-speed data signals transmitted on plural channels, and the resulting low-speed data signals are subsequently processed and recombined into the original signals transmitted on a single transmission channel.
2. Description of the Prior Art
Video signals may be digitally processed in known manner for e.g. noise reduction or enhancement operations. When the standard television video signals of the NTSC system, for instance, are processed digitally, since the frequency range of the video signals is approximately 4 MHz, the sampling clock frequency of approximately 10 MHz suffices. In this case, digital signal processing may be effected with the aid of the conventional transistor-transistor logic (TTL).
With recent progress in the art of high-resolution, high-quality or high-definition video systems making use of 1,125 scanning lines, it has become necessary to digitally process these high-resolution video signals. The frequency range for these high-resolution video signals is as broad as e.g. 25 to 30 MHz so that the sampling clock frequency used for digitally processing these broadband video signals reaches about e.g. 70 to 80 MHz. In such case, it is practically impossible to make use of standard transistor-transistor logic elements for signal processing. This has led to using emitter coupled logic (ECL, sometimes known as CML) or the like high-speed elements, or to converting sampling high-speed data into low-speed signals and digitally processing them with the use of TTLs or the like.
While the high-speed element such as ECL enables the high-speed sampling data to be directly processed digitally in an advantageous manner, the high-speed element such as ECL is generally expensive and consumes much power thus causing difficulties in heat dissipation. In addition, read-only memories (ROMs) or random access memories (RAMs) frequently used for signal processing are low-speed elements and usually of the TTL interface type so that they are difficult to interface with the ECLs or the like high-speed elements.
It is also known in the art that the high-speed data signals obtained by sampling these broadband video signals such as the aforementioned high-resolution video signals are converted into low-speed data signals, which signals are then processed with the aid of conventional TTLs. In this case, the video signal processing circuit of the standard television system, such as NTSC system, may be used without any substantial modifications, while interfacing with memory circuits or the like is also facilitated.
In converting the high-speed sampling data signals, such as high-resolution video signals, into low-speed signals, sampling data groups each consisting of N input data are converted by serial-to-parallel conversion methods to N-channel or N-phase data for reducing the clock frequency to 1/N times the original clock frequency. However, since the data of a given channel are composed of the original sampling data taken at the pitch of 1 per N consecutive data, the parallel N-channel data present discontinuities in the respective channels, thereby complicating subsequent signal processing operations. Thus, in the case of the two-dimensional image processing in general, such as noise reduction or dropout compensation, the data of the vertically or horizontally adjoining pixels on the raster are used occasionally. However, since the data of the neighboring or consecutive pixels on the raster are not available in the same channel, it becomes necessary to exchange data between the channels, which complicates signal processing. In the ensuing step of recombining the processed low-speed data signals, it has been customary to carry out separate time-axis restoration within the respective channels and to effect commutation between the channels by a switch circuit for reestablishing the signal sequence on the original channel. The circuit design is complicated because of complicated timing control involved in time-axis restoration between the respective channels and changeover of the switch circuits. In addition, since data coupling to the respective channels is effected in this manner by the switch circuit, signal processing is inevitably affected by noises or data discontinuities.